To provide a memory controller capable of avoiding access concentrating on a portion of a storage area in a flash memory while accelerating an accessing speed to the flash memory by using a virtual block.
A memory controller 3 distributes a plurality of sector areas with logic addresses continuing to a plurality of logic zones in a logic block unit, also associates a plurality of physical zones in flash memory chips 2-0 and 2-1 with each other and allocates logic zones to the plurality of associated physical zones. Under such as setting, a plurality of physical blocks selected from the plurality of associated physical zones by one at a time are virtually combined to thereby form a virtual block. A logic block is allocated to the virtual block. The capacity of an area included in the logic block is made to coincide with the capacity of a user area included in the virtual block.
KIDA KENZO
AZUMA AKIO
| JP2004508626A | 2004-03-18 | |||
| JP2005107601A | 2005-04-21 | |||
| JP2000181784A | 2000-06-30 | |||
| JP2003085037A | 2003-03-20 | |||
| JP2003015946A | 2003-01-17 | |||
| JP2004086300A | 2004-03-18 |
Shin Koizumi
Akiko Ichikawa
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