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Title:
MEMORY CONTROLLER AND FLASH MEMORY SYSTEM EQUIPPED WITH MEMORY CONTROLLER AND METHOD FOR CONTROLLING FLASH MEMORY
Document Type and Number:
Japanese Patent JP2008243156
Kind Code:
A
Abstract:

To provide a memory controller capable of avoiding access concentrating on a portion of a storage area in a flash memory while accelerating an accessing speed to the flash memory by using a virtual block.

A memory controller 3 distributes a plurality of sector areas with logic addresses continuing to a plurality of logic zones in a logic block unit, also associates a plurality of physical zones in flash memory chips 2-0 and 2-1 with each other and allocates logic zones to the plurality of associated physical zones. Under such as setting, a plurality of physical blocks selected from the plurality of associated physical zones by one at a time are virtually combined to thereby form a virtual block. A logic block is allocated to the virtual block. The capacity of an area included in the logic block is made to coincide with the capacity of a user area included in the virtual block.


Inventors:
Mukoda, Naoki
Kida, Kenzo
Azuma, Akio
Application Number:
JP2007000086982
Publication Date:
October 09, 2008
Filing Date:
March 29, 2007
Export Citation:
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Assignee:
TDK CORP
International Classes:
G06F12/00; G06F12/02; G06F12/16
Domestic Patent References:
JP2004508626A2004-03-18
JP2005107601A2005-04-21
JP2000181784A2000-06-30
JP2003085037A2003-03-20
JP2003015946A2003-01-17
JP2004086300A2004-03-18
Attorney, Agent or Firm:
北澤 一浩
小泉 伸
市川 朗子