To improve generality and extendibility by allowing the device to easily correspond to memories whose specifications are different.

This device is provided with a data buffer 36 having a rising buffer 42, a falling buffer 43 and a mode control circuit 41, and a mode switching signal from an outside part is supplied to the mode control circuit 41, and a clock signal and a data strobe signal are supplied. The clock signal is supplied only to the rising buffer 42 in an SDRAM mode under the control of the mode control circuit 41, and data are fetched at the rising edge of the clock signal in the rising buffer 42 so that the transferring timing of the data can be controlled. Also, the data strobe signal is supplied to both the rising buffer 42 and the falling buffer 43 in a DDR mode under the control of the mode control circuit 41, and the data are fetched at the rising edge of the data strobe signal in the rising buffer 42, and the data are fetched at the falling edge of the data strobe signal in the falling buffer 43 so that the transferring timing of the data can be controlled.