To prevent refresh operation from stopping even when a system reset signal is inputted by a simple circuit.

A system reset signal and a system clock are inputted to the first DFE 121 of a reset circuit 110 for outputting a reset signal to a refresh circuit of a memory controller. An output of the first DFE 121 and the system clock are inputted to the second DFF 122. An output of the second DFF 122 is inputted to an INV 123. An output of the first DFF 121 and an output of the INV 123 are inputted to an AND 124 and, when the output of the first DFE 121 changes to '1', the reset signal is outputted and, when the output of the second DFF 122 changes to '1' at the next system clock irrespective of a length of the system reset signal to be inputted, the reset signal is disconnected.