Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JP2008084184
Kind Code:
A
Abstract:
To provide a memory controller to which high speed access is possible even in update of subdirectory entry.
The memory controller 12 controls a semiconductor memory 11, is equipped with a host interface 20 connected to a host device 2 to receive data and address from the host device 2, a holding circuit 25 which holds the address and control circuits 22-24 which detect information indicating a host directory from the data and when the information is detected, make the holding circuit 25 hold the address, wherein the control circuits 22-24 sequentially write the data in the same memory block when writing access is performed to the same address as the one held in the holding circuit 25.
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Inventors:
SUDA TAKANARI
Application Number:
JP2006265629A
Publication Date:
April 10, 2008
Filing Date:
September 28, 2006
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F12/02; G06F3/06; G06F3/08; G06F12/00; G06K19/07
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto