Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JP2016184233
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress a noise generated in transferring data to memory.SOLUTION: A memory controller C comprises: a writing part 6 that writes transfer data in memory; and a reading part 7 that reads the data from the memory. The writing part 6 includes a replacement unit 6b that, when the sequence pattern of "1" and "0" of a bit string constituting the data to be transferred to a signal line DL is a target pattern set as a replacement target, replaces the bit string with a replacement bit string in which noise is suppressed before writing the data to the memory. The reading part 7 includes a restoration unit 7b that restores an initial bit string from the replacement bit string read out from the memory.SELECTED DRAWING: Figure 2
Inventors:
NARUSE MINENOBU
Application Number:
JP2015063178A
Publication Date:
October 20, 2016
Filing Date:
March 25, 2015
Export Citation:
Assignee:
AISIN AW CO
International Classes:
G06F11/00; H03M5/14; H04L25/49
Domestic Patent References:
| JP2008102705A | 2008-05-01 | |||
| JP2012098777A | 2012-05-24 | |||
| JP2015015540A | 2015-01-22 | |||
| JP2011015322A | 2011-01-20 | |||
| JP2016167125A | 2016-09-15 | |||
| JP2016184234A | 2016-10-20 |
Foreign References:
| WO2012120813A1 | 2012-09-13 |
Attorney, Agent or Firm:
Patent business corporation r&c
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