Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JP3563340
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide single address mode DMA transfer matched to the specification of a low speed memory as a transfer target while securing a high speed transfer rate in CPU access.
SOLUTION: The memory controller is provided with a wait setting register 11 to preset the number of waits when accessing an external memory from a CPU, a wait setting register 12 for DMA transfer to preset the number of waits in single address DMA transfer from a memory for high speed operation to a memory for low speed operation among the external memories from the CPU, a selector 13 for selectively outputting the number of waits in either the wait setting register 11 or wait setting register 12 for DMA transfer corresponding to a single address DMA transfer request DMA-REQ and a memory access request M-REQ and a memory access control signal generating circuit 14 for generating and outputting a memory access cycle, in which the number of waits selected by the selector 13 is inserted.
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Inventors:
Minoru Yoshinaga
Application Number:
JP2000330155A
Publication Date:
September 08, 2004
Filing Date:
October 30, 2000
Export Citation:
Assignee:
NEC Microsystems, Inc.
International Classes:
G06F13/10; G06F12/00; G06F13/28; G06F13/42; (IPC1-7): G06F13/42; G06F12/00; G06F13/10; G06F13/28
Domestic Patent References:
| JP11143826A | ||||
| JP10333975A | ||||
| JP4241056A | ||||
| JP9180438A | ||||
| JP11070706A |
Attorney, Agent or Firm:
Tatsuo Tokumaru