To provide a memory control unit capable of efficient data transmission and reception, having a low power consumption mode such as self-refresh by means of a clock enable signal, in addition to refresh, in case that the memory being connected is a synchronous DRAM, and capable of efficiently performing the refresh and the self-refresh.

The memory control unit includes a first buffer (command queue) 13 capable of storing at least one set of commands output from a circuit 30 for arbitrating a plurality of memory access request sources 50-5n, a second buffer (command buffer) 11 capable of storing the commands output from the above first buffer, a first control circuit (state machine) 12 for controlling data transmission and reception to/from the memory, based on the above second buffer, and a second control circuit (command monitoring circuit) 14 for control the second buffer by the first buffer, based on the first control circuit and the contents of the first buffer and the second buffer. The second control circuit 14 compares the commands (addresses) stored in the first and the second buffers and selects one.

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