メモリコントローラ - Thomson Licensing

Title:

メモリコントローラ

Document Type and Number:

Japanese Patent JP5005350

Kind Code:

B2

Abstract:

The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

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Inventors:

Nige Meyer Tim
Brunet Thomas
Frying man rotar

Application Number:

JP2006543402A

Publication Date:

August 22, 2012

Filing Date:

November 15, 2004

Export Citation:

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Assignee:

Thomson Licensing

International Classes:

G06F12/00; G06F12/02; G06F12/06; G06F13/18

Domestic Patent References:

JP2002288037A
JP10312333A
JP2002328837A
JP2000172560A
JP2002063131A
JP2001356961A
JP2001175530A

Attorney, Agent or Firm:

Yoshikazu Tani
Kazuo Abe

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