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Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPH0272446
Kind Code:
A
Abstract:

PURPOSE: To decrease the referring frequency to a memory by sending immediately some necessary pieces of those data read out of the memory with no intervention of a data holding means.

CONSTITUTION: The 8-byte data read out of a memory 13 are inputted to a memory reading register MDR15 and a selector 17. While the 8-byte data read out of a memory 14 are inputted to an MDR16 and a selector 18. The selector 17 selects the data lines 13a and 15a, and the selector 18 selects the data lines 14a and 16a respectively. Then an aligner 19 shift cyclically the input 16-byte data to the right or the left by an appropriate extent and outputs the 8-byte data of the left half. Thus it is possible to decrease the reading frequency of the same part of a memory and to decrease the memory reference frequency.


Inventors:
TANAKA ATSUSHI
WATANABE TAKESHI
WATABE YASUO
NAGAI SEIJI
Application Number:
JP22343588A
Publication Date:
March 12, 1990
Filing Date:
September 08, 1988
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F9/34; G06F12/04; G06F12/06; (IPC1-7): G06F9/34; G06F12/04
Attorney, Agent or Firm:
Akita Haruki



 
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