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Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPS6132153
Kind Code:
A
Abstract:

PURPOSE: To relieve the load of hardware by providing a fault location classifying information generating circuit and a faulty location classification register holding faulty location classification information formed by the said circuit and displaying the content.

CONSTITUTION: When an error is detected by a memory controller 3, it is registered in a faulty location holding register in a faulty location display circuit 13 and the information is transmitted to a maintenance diagnostic device 5. A faulty location classification information generating circuit 14 takes logical operation for the content of a faulty location storage register at each classification unit, classifies it and outputs the result to a faulty location classification register 15. The content of the faulty location classification register is displayed directly on each device or displayed via a maintenance diagnostic device 5.


Inventors:
OMORI YUZO
Application Number:
JP15347484A
Publication Date:
February 14, 1986
Filing Date:
July 24, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/16; G06F11/00; G06F11/22; (IPC1-7): G06F11/00; G06F12/16
Domestic Patent References:
JPS57762A1982-01-05
JPS5933559A1984-02-23
JPS5420625A1979-02-16
Attorney, Agent or Firm:
Toshi Inoguchi



 
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