To surely write data from an analog-digital converting circuit(ADC) to a DRAM and read it out by allowing a CPU to check a flag in a register after reading data out of the DRAM and reread data out of the DRAM only when the writing operation of the ADC is overlapped with.

Digital data outputs from ADCs 1A and 1B are written to the DRAM 10 and read out. The register 11 stores a write enable signal for data writing to the DRAM 10 and a read signal 7a for data reading from the DRAM 10 and generates a flag 11a when the write enable signal 5c and read signal 7a overlap with each other. The CPU 7 when reading in the flag 11a rereads the data out of the DRAM 10. Consequently, even when the large- capacity DRAM 10 is used, the simple register 11 is added to surely read the written data out.