PURPOSE: To decrease the time required for memory transfer, by performing simultaneous readout/write and utilization of a bus line in time division for a plurality of addresses.

CONSTITUTION: In transferring data from a data memory M1 to a M2, a transfer controller C1 decides the address of the memory M1, transmits it to an address bus AB and transmits control signals AC1 and BC1WBCj. Buffer registers B1W Bj separates a bus line DB with the signals BC1WBCj to be a data reception mode. All memory cells connected to one address control line selected out of address control lines UA1WUAm of memory cells MS1-1WMSn-m transmit data on the bus line DB and store the data to the corresponding registers B1WBj. When the readout is finished, the controller C1 makes connection control of the bus line to a controller C2, controls the buffer registers B1WBj to Bj+1WBi. Next, the C1 selects the address control line of the memory M2, transmits a signal to a readout/write control line RW and writes the data in the Bj+1WBi to the memory cells.