Title:
メモリ装置及びその制御方法
Document Type and Number:
Japanese Patent JP7030942
Kind Code:
B2
Abstract:
According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.
Inventors:
Shinichi Kanno
Application Number:
JP2020199507A
Publication Date:
March 07, 2022
Filing Date:
December 01, 2020
Export Citation:
Assignee:
Kioxia Co., Ltd.
International Classes:
G06F12/02; G06F12/00
Domestic Patent References:
| JP2014225197A | ||||
| JP2011090496A | ||||
| JP2013191174A | ||||
| JP2012123499A | ||||
| JP2011128998A | ||||
| JP2015529917A |
Foreign References:
| WO2014185037A1 | ||||
| US20160147652 | ||||
| WO2011048738A1 | ||||
| US20130007352 | ||||
| WO2014031799A1 | ||||
| US20130246688 | ||||
| US20140281338 | ||||
| WO2011074712A1 | ||||
| US20140258601 |
Attorney, Agent or Firm:
Suzue International Patent Office