Title:
MEMORY DEVICE AND ITS EVALUATION METHOD
Document Type and Number:
Japanese Patent JP3914534
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide particular performance data that are not generally obtained by a large-scale integrated testing method by evaluating the performance characteristic of each memory cell in particular about a random access memory cell.
SOLUTION: The present invention provides an on-chip circuit and a testing method which evaluate transistor electric charge transfer performance and electric charge storage capability of a DRAM cell in an real operating environment. The on-chip circuit and the testing method can evaluate deterioration of a cell transfer device by a MOSFET deterioration mechanism that becomes active at the time of electric charge transfer or storage in an operating state or burn-in state. The on-chip circuit forces and senses voltage in each DRAM storage capacitor, displays each storage capacitor charge leakage rate and enables a pulse testing method for calculating an electric charge transfer rate between a bit line of the DRAM cell and the storage capacitor.
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Inventors:
Guessepe La Rosa
Alvin W Strong
Alvin W Strong
Application Number:
JP2003403813A
Publication Date:
May 16, 2007
Filing Date:
December 02, 2003
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G01R31/28; G11C29/06; G11C11/401; G11C29/00; G11C29/50; H01L21/8242; H01L27/108; (IPC1-7): G11C29/00; G01R31/28; G11C11/401; H01L21/8242; H01L27/108
Domestic Patent References:
| JP10199298A | ||||
| JP2001057081A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno
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