MEMORY DEVICE AND MEMORY SYSTEM

Title:

MEMORY DEVICE AND MEMORY SYSTEM

Document Type and Number:

Japanese Patent JP2023045879

Kind Code:

A

Abstract:

To improve characteristics of a memory device.SOLUTION: A memory device 2 according to an embodiment stores erase strength information regarding erase strengths of multiple erase voltages in an erase operation; stores erase loop number information regarding the number of erase operations in an executed erase sequence; stores a voltage information table for a plurality of voltages applied to first and second word lines during the erase operation; and determines voltages to be applied to the first and second word lines based on the erase strength information and the erase loop number information using the voltage information table. When the erase operation of a first erase sequence Seq1 is performed, first voltage is applied to each of the first and second word lines. When the erase operation of a second erase sequence Seq2 is performed on first and second blocks, the first voltage is applied to the first word line and second voltage different from the first voltage is applied to the second word line.SELECTED DRAWING: Figure 13

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Inventors:

FUJIMORI TAKUMI
SUNADA TETSUYA
SHIRAKAWA MASANOBU
YAMADA HIDEKI

Application Number:

JP2021154486A

Publication Date:

April 03, 2023

Filing Date:

September 22, 2021

Export Citation:

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Assignee:

KIOXIA CORP

International Classes:

G11C16/14; G11C16/16

Attorney, Agent or Firm:

Patent Attorney Corporation Suzue Patent General Office

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