Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2019054206
Kind Code:
A
Abstract:
To provide a memory device capable of improving integration degree.SOLUTION: A memory device includes multiple word lines laminated in a third direction orthogonal to a first direction and a second direction, multiple main bit lines including a first main bit line, and elongating in the second direction, multiple transistors including first and second transistors, where the channel width in the first direction of the first and second transistors is wider than the width of the multiple main bit lines in the first direction, a first sub-bit line group including a first sub-bit line electrically connected with the first main bit line while sandwiching the first transistor, and a second sub-bit line electrically connected with the first main bit line while sandwiching the second transistor and adjoining the first sub-bit line, where a segment connecting the first and second sub-bit line virtually intersects the second direction, and including multiple sub-bit lines elongating in the third direction, and a resistance change layer provided between the multiple word lines and the multiple sub-bit lines.SELECTED DRAWING: Figure 3
Inventors:
OKAJIMA MUTSUMI
Application Number:
JP2017178984A
Publication Date:
April 04, 2019
Filing Date:
September 19, 2017
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H01L21/8239; H01L27/105; H01L45/00; H01L49/00
Attorney, Agent or Firm:
Tetsuma Ikegami
Akira Sudo
Masahiro Takashita
Mitsuyuki Matsuyama
Akira Sudo
Masahiro Takashita
Mitsuyuki Matsuyama