PURPOSE: To attain high-speed continuous accesses with a memory device of large capacity by distributing 2-dimensionally the memory chips and giving control to selection of these chips so that the same chip does not receive the continuous accesses in a continuous access mode.

CONSTITUTION: Each optional lower bit not higher bit of the row/column addresses is decoded for selection of a memory chip at a high-speed access control part 13. In a continuous access mode the chips are selected one by one. In this case, the limit of the holding time can be ignored for the control signal since the continuous accesses is avoided with the same chip. Then the control signal which are delayed in response to the highest timing with which the row-column address can be fetched are allocated orderly in both row and column directions for each memory chip. Thus the cycle time can be minimized.