PURPOSE: To obtain a nonvolatile memory device with no back-up of a power supply which attains a high-speed access, by loading data to the 2nd high-speed and volatile storage means from the 1st storage means to which data are stored fixedly in an initialization mode.
CONSTITUTION: The data which are treated in a nonvolatile way are stored in a ROM 1. A RAM 2 stores the data processed by a system and loaded from the ROM 1 and is capable of a high-speed access. A control part 3 controls an address generating circuit 4 via a signal line 34 and delivers a data reading address to the ROM 1. At the same time, the part 3 delivers the address of the RAM 2 for writing data to a multiplexer 5. Then the part 3 delivers the read and write signals RD and WR with the timing corresponding to each address signal. Thus data are written to the RAM 2 from the ROM 1.
JPH05100945 | MEMORY ACCESS DEVICE |
JPS61256458 | INFORMATION TRANSFER SYSTEM |
JP3444154 | MEMORY ACCESS CONTROL CIRCUIT |
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