Title:
メモリデバイスおよびメモリデバイスのための構成方法
Document Type and Number:
Japanese Patent JP5749860
Kind Code:
B2
Abstract:
A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.
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Inventors:
Radoki, William Henry
Valli, Tomaso
Incarnati, Michele
Valli, Tomaso
Incarnati, Michele
Application Number:
JP2014525049A
Publication Date:
July 15, 2015
Filing Date:
July 31, 2012
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
G11C16/06; G06F12/16; G11C16/02; G11C16/04; G11C29/42
Domestic Patent References:
| JP2009282923A | ||||
| JP10177797A | ||||
| JP2003131954A |
Foreign References:
| WO2003085676A1 |
Attorney, Agent or Firm:
Nomura Yasuhisa
Yoshiyuki Osuga
Yoshiyuki Osuga