Title:
不良ビットを管理するメモリ・デバイス、メモリ・システム、および、その実装方法
Document Type and Number:
Japanese Patent JP7116376
Kind Code:
B2
Abstract:
A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
Inventors:
Wardage, daniel
Deblosse, John, Kenneth
Deblosse, John, Kenneth
Application Number:
JP2019568623A
Publication Date:
August 10, 2022
Filing Date:
June 11, 2018
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G11C29/44; G11C29/00
Domestic Patent References:
| JP2008186460A | ||||
| JP2002133894A | ||||
| JP11175409A |
Attorney, Agent or Firm:
Tadashi Taneichi