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Title:
MEMORY DIAGNOSIS CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6172346
Kind Code:
A
Abstract:

PURPOSE: To reduce greatly the time needed for diagnosis of various memories and also to attain the reduction of load in an execution mode of memory diagnosis as well as the improvement of the memory diagnosis processing efficiency, by providing an autonomous diagnosis function of memory into a controller to be diagnosed.

CONSTITUTION: When a processor memory RAM within an SWC is diagnosed by an MCP, the MCP sends an automatic test order for processor memory to the SWC. Thus a CPU executes autonomously a collation test to a desired data pattern through read/write operations of all available address areas within an RAM area and stores the result of this test to an ANSQ. The MCP obtains the desired timing after transmission of a processor memory diagnosis command and sends an ANSQ reading order to know the result of the diagnosis of the processor memory. In the diagnosis mode of an SCMP, an HCM and SCMS within a TDNW, the MCP designates only the type of a memory and sends a diagnosis command to the SWC. While the CPU within the SWC monitors the contents of an ORDQ like the detection mode of the processor memory diagnosis command and then detects a diagnosis command.


Inventors:
HARIMOTO KOUICHI
IIDA TETSUO
Application Number:
JP19411184A
Publication Date:
April 14, 1986
Filing Date:
September 17, 1984
Export Citation:
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Assignee:
NEC CORP
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F12/16; G06F11/22; (IPC1-7): G06F11/22; G06F12/16
Domestic Patent References:
JPS5923944A1984-02-07
JPS5776640A1982-05-13
JPS5839350A1983-03-08
Attorney, Agent or Firm:
Uchihara Shin