PURPOSE: To write on a memory cell near the input terminal side at a high speed and to read from a memory cell near the output terminal side at a high speed.

CONSTITUTION: A bit line BL(R)1 for reading out the part of memory cells M0-MU-1 having '0' to U-1 addresses and a bit line BL(R)2 for reading out the part of memory cells MU-MU+V-1 having U to U+V-1 addresses are divided by means of a try state buffer(BUF) 7. Similarly, bit lines for writing are divided into BL(W)1, BL(W)2 and a buffer(BUF) 8 is set in between. Consequently, e.g. at the time of reading the memory cells M0-MU-1 of 0-(U-1) addresses, only the bit line BL(R)1 for reading is charged. The bit line BL(R)1 for reading is connected to a power source Vcc through a resistor 6 in order to pre-charge and the bit line BL(R)2 for reading is connected to the power source Vcc through a resistor 9.