Title:
MEMORY DUMP SYSTEM
Document Type and Number:
Japanese Patent JPS58115561
Kind Code:
A
Abstract:
PURPOSE: To perform the dump processing certainly, by starting a reset signal generating circuit after a non-masking interrupt signal is continued for a prescribed time and detecting the nonmasking interrupt signal when a program is restarted.
CONSTITUTION: When a memory dump key 1 is depressed, the signal obtained from a key receiver 2 is inputted to a non-masking interrupt signal NMI generating circuit 3. The circuit 3 is turned on and is held in a certain level for a prescribed time; and a reset generating circuit 4 is activated when the circuit 3 is turned off, and a processing device is reset by the output. Thus, the NMI signal is detected when the program is restarted. Consequently, the dump processing is performed certainly.
Inventors:
TANAKA TAKAO
Application Number:
JP21307481A
Publication Date:
July 09, 1983
Filing Date:
December 29, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F12/16; G06F9/48; G06F11/00; G06F11/34; G06F13/00; G11C29/00; (IPC1-7): G06F11/00; G06F13/00; G11C29/00
Attorney, Agent or Firm:
Akira Yamatani