PURPOSE: To eliminate the need for an equivalent circuit at the external part of a memory element by incorporating a parity generating and error detecting circuit in the memory element.

CONSTITUTION: When a data input is instructed by an input and output control 13, a parity is added to the data input through an input data controller 4, a sense switch 5 in the parity generating and error detecting circuit 8 and written to a memory cell designated by applied row/column addresses 11, 14. At the time of instructing a data output, the data having the parity read by the memory cell instructed by the applied row/column address is checked by the circuit 8, the presence and the absence of the error and a data output 15 passing through the switch 5 and an output data controller 9 are sent externally.