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Patent Searching and Data


Title:
MEMORY ERROR DETECTING/CORRECTING METHOD
Document Type and Number:
Japanese Patent JPH03290745
Kind Code:
A
Abstract:

PURPOSE: To correct a memory error with application of a parity check system by usually performing the horizontal parity check to the memory read data and then carrying out the vertical parity check only when a parity error is detected.

CONSTITUTION: A memory 11 is logically divided into blocks BL0 - BLN-1 in the address direction, and a parity bit is added to each block in both horizontal and vertical directions. In a read access state of the memory 11, the horizontal parity check is carried out. If a parity error is detected in the horizontal parity check, the vertical parity check is carried out to the corresponding block. If a parity error is detected in the vertical parity check, the bit position shows a position of an error bit in the word data received a memory read access. Thus the error is easily corrected on the basis of the parity check.


Inventors:
MIYAO MOTOHISA
Application Number:
JP9203090A
Publication Date:
December 20, 1991
Filing Date:
April 09, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F12/16; G06F11/10; (IPC1-7): G06F12/16
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)