Title:
MEMORY IC TEST SYSTEM
Document Type and Number:
Japanese Patent JP2808988
Kind Code:
B2
Abstract:
PURPOSE: To automatically detect redundancy availability after the wiring of a redundant circuit is cut by using laser or the like, in a memory IC having a redundant circuit.
CONSTITUTION: The test results of a preliminary electric test for redundancy add the test results of a final electric test after the wiring of a redundant circuit is cut by using laser or the like are transferred to a computer 5 on line via a communication cable 6. The computer 5 performs operation on the basis of the test results, and automatically calculates redundancy availability. The calculated redundancy availability is transferred to an IC tester or the like which is performing the final electric test, and displayed on a printer or a CRT monitor.
Inventors:
KIKUCHI TOSHIHIKO
Application Number:
JP16368092A
Publication Date:
October 08, 1998
Filing Date:
May 29, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/26; G01R31/28; G11C29/00; G11C29/56; H01L21/66; H01L21/82; H01L27/10; (IPC1-7): H01L21/82; G01R31/26; G01R31/28; G11C29/00; H01L21/66; H01L27/10
Domestic Patent References:
| JP59207497A | ||||
| JP429076A | ||||
| JP554694A | ||||
| JP5282892A |
Attorney, Agent or Firm:
Seiichi Kuwai
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