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Title:
MEMORY IC
Document Type and Number:
Japanese Patent JPH04312965
Kind Code:
A
Abstract:

PURPOSE: To increase a memory capacity in the same package size.

CONSTITUTION: A printed board 7 in which wiring patterns are formed on both front and rear surfaces, semiconductor memory cells 2a disposed on the front surface side of the board 7, and semiconductor memory cells 2b disposed on the rear surface side of the board 7, are provided. A lead frame 3 connected to a chip enable terminal of the cell 2a and a lead frame 3 connected to a chip enable terminal of the cell 2b are individually provided on the board 7, and a lead frame 3 connected commonly to a terminal except the enable terminal of the cells 2a, 2b is provided. The cells 2a, 2b and the board 7 are sealed with synthetic resin 4. The cell 2a or 2b is selected by selecting the frame 3 connected to the enable terminal, and data are written in or read from the selected cell through the frame 3 commonly connected to the other terminal.


Inventors:
MORI YOSHIHIDE
SHINOHARA TAKAYUKI
Application Number:
JP6577591A
Publication Date:
November 04, 1992
Filing Date:
March 29, 1991
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
B42D15/10; G06K19/077; G11C17/00; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L25/065; G11C17/00; B42D15/10; H01L25/18; H01L25/07
Attorney, Agent or Firm:
Mamoru Takada (1 person outside)



 
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