PURPOSE: To improve burst transfer performance.

CONSTITUTION: An address which is inputted on a time-division basis from a terminal 1 is set in a cumulative adding register 24 and an increment register 21 and a burst transfer mode is started. A row address is inputted from a terminal 1 and one row of a memory array 7 is read out to a sense amplifier 6. The high-order (n) bits of the register 24 are passed through a column address decoder 5 to access one cell of the sense amplifier 6, and data are read out of the cell in read mode and written in the cell in write mode. An adder 22 adds the contents of the registers 24 and 21 together, the addition result is stored in the register 24 again to perform the cumulative addition of the column address. Consequently, the high-order (n) bits of the column address select a 2nd cell of the sense amplifier 6. Consequently, when it is considered that the register 24 is a real number consisting of integer part (n) bits and (n) bits below the decimal point, the column address uniformly increases or decreases at constant intervals of the real number specified by the register 21 and a sequence of memory cells indicated by the integer part is accessed in order.