To provide a memory writing initial activation control circuit capable of properly detecting an anomaly of any state of a memory circuit 1.

When a power source is turned on, all pieces of data read from the memory circuit 1 are written again into the memory circuit 1 from a memory input switching circuit 7. At the same time, a parity sending circuit 5 generates parity bits of the pieces of data to be written in the memory circuit 1, a parity reversal control circuit 9 controlled by control of an initial control circuit 4 reverses the parity bits, and the reversed parity bits are written in a parity region of the memory circuit 1. All pieces of data are read from the memory circuit 1, an alarm generating state is provided, all the pieces of the data are written again into the memory circuit 1, normal parity bits are written into the memory circuit 1, and the alarm generating state is terminated.