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Title:
MEMORY INITIAL SETTING SYSTEM
Document Type and Number:
Japanese Patent JPS5580896
Kind Code:
A
Abstract:

PURPOSE: To prevent the misrecognition of the memory fault by writing the specified data into the all addresses or the specified area of the volatile memory before or after loading of the initial program.

CONSTITUTION: The total number of the address into which 0 is to be written is set first at working register WR301, and then delivered through signal line 302 when the contents of register WR301 becomes zero. Then the address into which 0 is written first is set, and memory address register 102 and memory buffer register 103 are selected through register selection part 204. And the 0-value is designated to arithmetic circuit 111 via control signal part 205, and then the 0-value is written into the address of register 102. After this, 1 is subtracted from the value of WR301, and the necessary process is repeated until the fact is detected that the value of WR301 becomes zero. In such way, 0 is written into all addresses into which 0 is not written by the initial program load.


Inventors:
FUJITA HIROSHI
Application Number:
JP15206378A
Publication Date:
June 18, 1980
Filing Date:
December 11, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F9/22; G06F1/00; G06F1/24; G06F9/24; G06F12/00; G06F12/16; G11C29/00; (IPC1-7): G06F1/00; G11C29/00



 
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