PURPOSE: To enable a semiconductor memory to be shortened in failure analysis time, lessened in inspection cost, and improved in analysis efficiency.

CONSTITUTION: When the fail data of a semiconductor memory 2 to be inspected is written in a fail memory 42, a write address to the fail memory 42 is controlled by the use of an arithmetic and control circuit 41 based on the address signal of the semiconductor memory 2, the output data Dfi of a comparison circuit 3 is written in the fail memory 42 and stored corresponding to its address. The above process is carried out in real time, whereby a time required for acquiring necessary processing data can be shortened.