Title:
MEMORY INTEGRATED CIRCUIT FOR VIDEO DISPLAY
Document Type and Number:
Japanese Patent JP3191468
Kind Code:
B2
Abstract:
PURPOSE: To speedingly process a rectangular region transfer of video data.
CONSTITUTION: When the data, which are equivalent to one line stored in the transfer origin region of a memory cell array 1, are transferred to a transfer destination region, the data, which are equivalent to one line and are read from the transfer origin region, are selected by a transfer gate 6 in accordance with input output select signals 101 and are outputted to serial ports 7a to 7d or an arithmetic and logic circuit 9. The circuit 9 performs arithmetic operations instructed by arithmetic operation select signals 104 against the one line data from one of the serial ports 7a to 7d selected by a selector 8 and the one line data from one of the other serial ports 7a to 7d or the data which are equivalent to one line and inputted from the memory cell array 1 through the transfer gate 6. The results of the operations are outputted to the memory cell array 1 or the serial ports 7a to 7d through the transfer gate 6.
Inventors:
Kiyoto Miyazawa
Application Number:
JP2070893A
Publication Date:
July 23, 2001
Filing Date:
January 13, 1993
Export Citation:
Assignee:
NEC
International Classes:
G06F3/153; G06F12/04; G09G5/00; G11C11/401; (IPC1-7): G11C11/401; G06F3/153; G06F12/04
Domestic Patent References:
| JP4230546A | ||||
| JP6271386A |
Attorney, Agent or Firm:
▲柳▼川 信