Title:
MEMORY INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH05314777
Kind Code:
A
Abstract:
PURPOSE: To reduce current consumption at a writing and a reading operation time.
CONSTITUTION: This circuit is provided with a circuit 3 detecting the change of an address signal and the change of a write data signal and outputting a pulse, and a pulse control circuit 5 adjusting the pulse width of the pulse generated in the circuit 3. The selection intervals of a word line, a digit line selection circuits are decided by the pulse-width-adjusted pulse and current is limited so as not to flow without the interval and the current is reduced.
Inventors:
YAMADA YASUMASA
Application Number:
JP11559892A
Publication Date:
November 26, 1993
Filing Date:
May 08, 1992
Export Citation:
Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C11/413; (IPC1-7): G11C11/413
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)