PURPOSE: To obtain the memory jig to efficiently check/repair a memory by supporting the grasp of a condition in the case of memory error with simple configuration.

CONSTITUTION: Address signals A0-An of an outside memory system are fetched through a bus 1 and according to an outside parity error detection signal PE, the error address signals A0-An of the bus 1 are successively stored in an FIFO memory 2. Then, the first read error address signals A0-An in the FIFO memory 2 are displayed at a display part 3 according to an m-ary method, a read pulse RP of the FIFO memory 2 are generated by a switch 4, and error addresses are successively displayed.