MEMORY LAYOUT FORMING METHOD - MITSUBISHI ELECTRIC CORP

Title:

MEMORY LAYOUT FORMING METHOD

Document Type and Number:

Japanese Patent JPH0210767

Kind Code:

A

Abstract:

PURPOSE: To realize automatic formation by arranging a small-scale memory cell or decoder cell regularly in the vertical direction.

CONSTITUTION: Four ROM/RAM cells and two decoder cells 7 are arranged with minimum spaces required such that the wirings 8 may be directed in the vertical direction of a semiconductor substrate, thus the ROM/RAM unit 4 of (a×4) words × b bits is realized. The size of the ROM/RAM designated by a user is input so as to determine the numbers of cells 6 and decoder cells 7 inside the unit 4, whereby the number of units required for realization of the size input is determined using this constituent unit so as to perform arrangement and wiring. By doing it in this way, the memory of an optional size can be automatically formed using a computer at the integration degree equivalent to the input design.

Inventors:

IIO KANAKO

Application Number:

JP16181888A

Publication Date:

January 16, 1990

Filing Date:

June 28, 1988

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP

International Classes:

H01L21/822; G06F17/50; H01L21/82; H01L27/04; H01L27/10; H01L27/118; (IPC1-7): G06F15/60; H01L21/82; H01L27/04; H01L27/10; H01L27/118

Attorney, Agent or Firm:

Masuo Oiwa (2 outside)

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