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Title:
MEMORY LOCK CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0520166
Kind Code:
A
Abstract:

PURPOSE: To decrease an idle time caused by waiting for the memory lock of a processor by constituting the system so that plural processors can lock simultaneously memory data of different addresses.

CONSTITUTION: At the time of locking memory data of an arbitrary address, processors 10, 20 request 'lock and read-out' to a memory device 80. The memory device 80 reads out data from a memory element 105, returns the data to the processors 10, 20, and thereafter, rewrites the data of the address to data whose parity is erroneous. Only the data of a locked address becomes a state of a parity error. The processors 10, 20 can decide whether the data of the address is locked or not by whether the parity error of the data returned from the memory device 80 exists or not.


Inventors:
BAN TSUTOMU
Application Number:
JP17644191A
Publication Date:
January 29, 1993
Filing Date:
July 17, 1991
Export Citation:
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Assignee:
SHIKOKU NIPPON DENKI SOFTWARE
International Classes:
G06F11/10; G06F12/00; G06F12/16; (IPC1-7): G06F11/10; G06F12/00; G06F12/16
Attorney, Agent or Firm:
Uchihara Shin



 
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