PURPOSE: To make it possible to directly read out a machine instruction and RAM data respectively by an instruction reading control device and a RAM data reading control device.
CONSTITUTION: The machine instruction reading control device 5 sends transfer and reading requests to/from a control circuit 12 for controlling an address in which RAM data are written to a read/write control device 6. The device 6 sends a read permission signal, the control circuit 12 transfers the address to a RAM data address bus 3 and RAM data are read out to a machine instruction reading control device 5 through a RAM data bus 4. The device 6 sends transfer and reading requests to/from a control circuit 11 for controlling an address in which a machine instruction is written to the device 5. The device 5 sends a read permission signal, the circuit 11 transfers the address to a machine instruction address bus 1 and the machine instruction is read out to the device 6 through a machine instruction data bus 2.
JPS60129856A | 1985-07-11 | |||
JPH01269128A | 1989-10-26 | |||
JPH02183331A | 1990-07-17 | |||
JPS599767A | 1984-01-19 | |||
JPS61272861A | 1986-12-03 |