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Patent Searching and Data


Title:
MEMORY REFERENCE SYSTEM
Document Type and Number:
Japanese Patent JPS5472923
Kind Code:
A
Abstract:

PURPOSE: To simplify a unit with the number of stages of an adder reduced, by finding a fixed address by enabling a simple control circuit to select the segment assignment part of the address part of instructions or the segment assignment part of an index register.

CONSTITUTION: This system is provided with instruction register 10 supplied with a memory reference instruction composed of index modification part X, segment assignment part SN1 and diaplacement part D, segment assignment part SN2 which refers on the basis of modification part X of the instruction supplied to register 10, and index register 11 consisting of index value (index). Further, this is equipped with control icircuit 13 which selects either assignment part SN1 of register 10 or assignment part SN2 of register 11 as segment assignment, and segment register 12 which is supplied with location value (r) by the segment assignment selected by circuit 13; and respective values are added by adders 14 and 15, and the addition value is used as the assignment address of the memory.


Inventors:
TANAKA AKIO
Application Number:
JP13987877A
Publication Date:
June 11, 1979
Filing Date:
November 24, 1977
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F12/10; G06F13/00; G11C7/00; (IPC1-7): G06F13/00; G11C7/00