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Title:
MEMORY REFRESH CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6013397
Kind Code:
A
Abstract:

PURPOSE: To reduce radiation noise and to suppress the power supply capacity of a device by preventing two or more memory units from simultaneous refresh operation in a memory system having the memory unit constituted of a dynamic RAM.

CONSTITUTION: After the memory unit 2 has obtained a refresh control right, the relation between a line B and a line C is adjusted by an arbiter 4 and then the refreshing operation is commanded to a timing control circuit through a line D. The timing control circit 3 sends a signal to the RAM 1 through a line E to execute the refreshing operation. After refreshing, the timing control circuit 3 initializes the arbiter 4 through the line D and outputs a refresh end pulse to a line A to count up the memory unit 2 by +1, initialize a refresh circuit 5 and restart the timer. Said refresh end signal is inputted to a gate 10 to initialize flip folps 6, 9. Thus, the simultaneous refreshing operation of two or more memory units is prevented, so that concentrical current flow is prevented.


Inventors:
KATOU HIDEAKI
Application Number:
JP12212183A
Publication Date:
January 23, 1985
Filing Date:
July 05, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/406; G11C11/34; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Uchihara Shin