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Title:
MEMORY SWITCH CHANNEL SYSTEM
Document Type and Number:
Japanese Patent JPS5549095
Kind Code:
A
Abstract:

PURPOSE: To reduce the whole package capacity by extending channels by introducing high-speed memories on occasion by making use of memories packaged initially, by constituting buffer memories by combining low-speed memories and high-speed memories.

CONSTITUTION: Data of a time slot on highway #1 is applied to block A of buffer memory 6, and data on highways #2 to #4 are to high-speed buffer memory 14 by way of high-speed multiplexer 12. Further, selector 11 supplied with the output of memory 6 and selector 11 connected to demultiplexer 15 supplied with the output of memory 14 are provided, and address access to memory block A and memory 14 is attained by holding memories 7. Memory block A on a channel system of this constitution is composed of low-speed memories 6 connected together in parallel and high-speed memory 14 is connected to this block A to constitute a buffer, thereby simplifying memory extension at the time of an increase in channel capacity.


Inventors:
MIYAYASU KENJI
Application Number:
JP12286578A
Publication Date:
April 08, 1980
Filing Date:
October 05, 1978
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04Q3/52; H04Q11/04; (IPC1-7): H04Q3/52



 
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