To shorten latency in a read operation from a nonvolatile memory.
A memory system 10 includes: a nonvolatile memory 11 for storing data; a buffer 15 for tentatively storing the data from the nonvolatile memory 11; a correction circuit 17 for correcting errors of the data from the buffer 15; a buffer 18 for tentatively storing the data from the correction circuit 17; a bus 20 for receiving the data from the buffer 18; a command sequencer group for issuing a plurality of commands for data transfer between the nonvolatile memory 11 and the bus 20; a command decoder group for decoding the plurality of commands and generating a plurality of control signals for controlling the data transfer; and an interruption circuit 21 for generating an interruption in a CPU 22 when a read error due to error correction incapability occurs. Even when the interruption is generated, the command sequencer group continues the data transfer from the nonvolatile memory 11.
| JPS62233861 | CANCEL CONTROL SYSTEM FOR MEMORY DEVICE |
| JP2001005614 | DISK DEVICE AND SERVER DEVICE |
| JPS61249153 | DATA PROCESSOR |
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen