To constitute a memory system in which a plurality of memory modules corresponding to different protocols are used and cascaded.
The memory system 100 is cascaded to a memory device by using the plurality of memory modules 102 etc. each having, each of the memory modules 102 including a buffer part which receives an access command or the like to the buffer it temporarily and determines whether the access command or the like is for access to the memory device or not. Each memory module 102 or the like has a conversion circuit which when receiving the access command or the like by the buffer part of the memory module and when it is determines that the access command and data access the memory device in the memory module to which the buffer part belongs, converts the access command or the like to an access command or the like recognizable by the memory device.
JP2006146390A | 2006-06-08 | |||
JP2005535038A | 2005-11-17 | |||
JP2004139552A | 2004-05-13 |
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