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Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2017045311
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a memory system capable of easily increasing the memory capacity.SOLUTION: A memory system of an embodiment includes: interface circuits 210 and 220 that recognize as a command a second command SI which is received immediately after a first or second chip select signal/CS1 or /CS2 is received; and first and second memory cell arrays 100-1 and 100-2. The interface circuits 210 and 220 and the first and second memory cell arrays 100-1 and 100-2 are packaged in an identical package. The interface circuits 210 and 220 access, when the first chip select signal/CS1 is asserted, the first memory cell array 100-1; and access, when the second chip select signal/CS2 is asserted, the second memory cell array 100-2.SELECTED DRAWING: Figure 4

Inventors:
NARAI YOSUKE
KITAZUME TOSHIHIKO
KADA KENICHIRO
TSUJI NOBUHIRO
KODERA SHUNSUKE
IWATA TETSUYA
FURUYAMA YOSHIO
TAKEDA SHINYA
Application Number:
JP2015167874A
Publication Date:
March 02, 2017
Filing Date:
August 27, 2015
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F12/06; G06F12/00
Domestic Patent References:
JP2015503169A2015-01-29
JP2011503760A2011-01-27
JP2002259322A2002-09-13
JP2003242044A2003-08-29
JP2002244932A2002-08-30
JP2015076109A2015-04-20
JP2007193811A2007-08-02
JP2012022541A2012-02-02
JP2016514320A2016-05-19
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Katsu Sunagawa
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi



 
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