Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2019160195
Kind Code:
A
Abstract:
To suppress a decrease in error correction efficiency.SOLUTION: A memory system of an embodiment includes a nonvolatile memory 2 including a memory cell array 20, and a memory controller 3 including a first ECC circuit and a second ECC circuit having a higher error correction capability than the first ECC circuit and reading data from the nonvolatile memory 2. The first ECC circuit corrects an error of the first read data read from the nonvolatile memory 2. When the first ECC circuit cannot correct the error, the memory controller 3 determines whether a hard error occurs in the memory cell array 20. When the hard error occurs in the memory cell array, the second ECC circuit executes error correction using second read data except a bit in which the hard error occurs.SELECTED DRAWING: Figure 19
Inventors:
TAKAHASHI EIETSU
Application Number:
JP2018049703A
Publication Date:
September 19, 2019
Filing Date:
March 16, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
G06F11/10; G11C16/04
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken