Title:
メモリシステム
Document Type and Number:
Japanese Patent JP4519923
Kind Code:
B2
Abstract:
A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.
Inventors:
Yasushi Nagatomi
Application Number:
JP2008051405A
Publication Date:
August 04, 2010
Filing Date:
February 29, 2008
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F12/00; G06F3/06; G06F3/08; G06F12/16
Domestic Patent References:
| JP2001291388A | ||||
| JP2004227486A | ||||
| JP2002318638A | ||||
| JP2008010607A | ||||
| JP2002007202A | ||||
| JP2006155479A |
Attorney, Agent or Firm:
Hiroaki Sakai