Title:
メモリシステム
Document Type and Number:
Japanese Patent JP6967986
Kind Code:
B2
Abstract:
According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.
Inventors:
Satoshi Kaburagi
Katsuya Ohno
Yutaka Katogi
Katsuya Ohno
Yutaka Katogi
Application Number:
JP2018012649A
Publication Date:
November 17, 2021
Filing Date:
January 29, 2018
Export Citation:
Assignee:
Kioxia Co., Ltd.
International Classes:
G06F12/02; G06F12/00; G06F12/06; G06F12/0875; G06F12/0895; G06F12/121
Domestic Patent References:
| JP2006119796A |
Foreign References:
| US20170068621 | ||||
| WO2015173889A1 |
Attorney, Agent or Firm:
Suzue International Patent Office