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Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JPH03138742
Kind Code:
A
Abstract:

PURPOSE: To quickly and easily initialize a memory cell, perform the initial test, and check the preservation state by adding a test circuit having a test address and data generating circuit, arithmetic circuit, etc., to a memory LSI.

CONSTITUTION: A test address and data generating circuit 13, an arithmetic circuit 14 which generates the check sum or the like of write data and read data at the time of test, a comparator 16 which compares the check sum of write data with that of read data, multiplexers 9 and 10 for switching between address and input/output data from the external and those for test, and a timing controller 18 which controls them are provided in the memory LSI. The memory LSI is automatically tested at the time of power-on without increasing the number of input/output pins. Thus, the test is performed in a short time.


Inventors:
INOUE AKIFUMI
Application Number:
JP27604089A
Publication Date:
June 13, 1991
Filing Date:
October 25, 1989
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F12/16; G11C29/10; G11C29/40; G06F11/10; (IPC1-7): G06F12/16
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)



 
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