PURPOSE: To make it possible to increase the speed of the operation of a memory unit having a selecting circuit which selects input from access sources, by receiving access requests from access sources and inputs accompanying them at the same time.

CONSTITUTION: Since selective signal 27 of arithmetic processor BPU shows "1" when access request 10 is made, selecting circuit 8 selects address 18 from processor BPU and sends it to output 20. While request 10 is set in register 4, output 20 of circuit 8 is also set in address register 9 by trigger signal 31. If register 4 is set at this time, output signal 31 of AND circuit 26 is changed into "0" from now on by signal 14, so the update of register 9 is inhibited to hold address 18 in register 9. Thus, the operation speed of the memory circuit can be increased by receiving an access request and address signal from processor BPU at the same time.