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Title:
METAL-IMPURITY INSPECTING WAFER AND METAL-IMPURITY INSPECTING METHOD USING WAFER THEREOF
Document Type and Number:
Japanese Patent JP2000040723
Kind Code:
A
Abstract:

To capture metallic contaminants in high sensitivity and effectively in the wafer processing step with which the surface of a wafer is cut out, by forming a polysilicon layer on the surface of an inspecting silicon substrate, wherein the surface layer has insulating property.

An insulating film 2 is formed on a single-crystal silicon wafer 1, which is not contaminated with metal. A polysilicon layer 3 is grown and deposited on the surface layer, and an inspecting ware 10 is formed. The mounting amount of the polysilicon layer 3 is made to be 10 μm or more, since the thickness of the degree that is not polished to the insulating film 2 in the polishing process is required. Then, the specified polishing is performed under the same polishing system and conditions as for a product wafer, and the metal impurities contaminated with the polishing process are captured. Then, the metal impurities contaminated in the polishing process are trapped in the vicinity of the interface of the insulating film 2 of the inspecting wafer 10 or in the polysilicon layer 3 after polishing. Therefore, the recovering rate of the metal impurities becomes high, and the detection sensitivity becomes high.


Inventors:
SASAKI TAMOTSU
KANETANI KOICHI
SAKURAI JUNICHI
Application Number:
JP20755798A
Publication Date:
February 08, 2000
Filing Date:
July 23, 1998
Export Citation:
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Assignee:
SHINETSU HANDOTAI KK
International Classes:
G01N23/223; G01N1/28; H01L21/02; H01L21/66; (IPC1-7): H01L21/66; G01N1/28; G01N23/223; H01L21/02
Attorney, Agent or Firm:
Masahisa Takahashi (1 person outside)